Section D — Registers, configuration, and software (20 points) 10. (6 pts) A register map shows a control register at address 0x00 with bits: bit 15 = reset (self-clearing), bit 12 = speed select (0=10/100, 1=1000), bit 8 = loopback enable. Describe initialization sequence after power-up to enable Gigabit mode, bring the device out of reset, and enable auto-negotiation. 11. (8 pts) Explain how MDIO/MDC transactions read a 16-bit register: outline preamble, start, opcode, PHY address, reg address, turnaround, and data phases. Give the bit lengths for each field per Clause 22. 12. (6 pts) Provide a short algorithm (pseudocode) to poll link status with exponential backoff: check up to 6 times, starting delay 100 ms doubling each attempt, stop early if link is up.
Section E — Reliability, testing, and compliance (10 points) 13. (5 pts) List five reliability or compliance tests (e.g., ESD, thermal cycling, humidity, S-parameter channel test, EMI) that the datasheet might reference, and give one acceptance criterion for each. 14. (5 pts) Describe how to interpret an eye diagram and bit error rate (BER) spec in the datasheet when qualifying a 1000BASE-T PHY.
Exam: KSZ80 OB S4LV02 — Advanced Technical Examination Instructions: Answer all questions. Show calculations and reasoning where applicable. Use SI units. Total points: 100.